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I have primarily a C++ background. I was tracking down a bug in some SystemVerilog code I am working on and was surprised to find what I thought was an object-copying assignment was actually a reference assignment. This simplified code shows what I mean:
for (int i = 0; i < max_num; ++i)
{
var cls_obj obj1;
obj1 = obj_array[i];
some_function(obj1); // modifies the object passed in
// at this point BOTH obj1 and obj_array[i] are modified.
// some other code goes here
}
I was expecting only obj1 to be modified. Is this because of the var keyword? How exactly does copy assignment vs. reference assignment work in SystemVerilog? I am having a hard time finding information from web searches.
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SystemVerilog and SystemC are the languages used for verification and hardware modelling. Both have features which are unique to each of them while some features are inherited from C++ language.
"<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators.
In the design verification role, SystemVerilog is widely used in the chip-design industry.
SystemVerilog is the most preferred language for the IP & Sub-system verification that demands constrained random verification. Also, it's an IEEE standard Hardware Design and Verification Language [HDVL] which can be used for both the RTL design and verification.
By default, function parameters in SystemVerilog are passed by value. However class handles are treated as values, so any class you pass into a function is effectively passed by reference. There is a built-in mechanism in the language to do a shallow copy when initializing a class object. This does a shallow copy.
By default, does SystemVerilog pass arrays by value or reference? int array [5] = ' {0,1,2,3,4}; some_function (array); // <-- value or reference? By default, SystemVerilog passes arrays by value, copying the entire array. It is recommended to pass arrays by reference whenever possible for performance reasons.
Let us discuss some of the major key differences between Verilog vs SystemVerilog: Hardware Description Language or HDL is used to model electronic systems in Verilog, whereas, in SystemVerilog, HDL helps to model, design, simulate, test, and implement electronic systems.
SystemVerilog deep copy copies all the class members and its nested class members. unlike in shallow copy, only nested class handles will be copied. In shallow copy, Objects will not be copied, only their handles will be copied. to perform a full or deep copy, the custom method needs to be added.
Class variables in SystemVerilog are references, or handles. Instances are only created when you use the new keyword.
So in your example, obj1 and obj_array[i] both refer (or point) to the same instance.
By default, function parameters in SystemVerilog are passed by value. However class handles are treated as values, so any class you pass into a function is effectively passed by reference.
There is a built-in mechanism in the language to do a shallow copy when initializing a class object.
Packet p1;
Packet p2;
p1 = new;
p2 = new p1;
This does a shallow copy. For objects only the handles are copied!
This is explained with examples in Chapter 8.11 of IEEE 1800-2009.
The var keyword does not have anything to do with the behavior you are seeing. In fact, I've never even seen or used var. According to the LRM this allows one to omit the type when declaring the variable. In you code, the type (cls_obj) is specified so I don't think its presence is doing any thing.
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