Syntax about chisel :Vec & Wire

Question

I am learing Chisel3.

I have some questions about the codes.

val myVec = Wire(Vec(5, SInt(width = 23)))  // Vector of 5 23-bit signed integers.

I thought if I declare a vector and I need to write "Wire",but I was wrong when I saw these codes.

class BigBundle extends Bundle {


 val myVec = Vec(5, SInt(width = 23))  // Vector of 5 23-bit signed integers.

 val flag  = Bool()
 // Previously defined bundle.

 val f     = new MyFloat

}

It punchs on my face suddenly,so I want to know when do I use "Wire"?

Thanks in advance.

Answer 1

The key here is the distinction in Chisel3 between "types" and "values."

Vec, Bundle, UInt, SInt, and Bool are examples of "types."

Wire, Reg, Input, Output, and Mem are examples of "values."

With BigBundle from the above:

class BigBundle extends Bundle {
  val myVec = Vec(5, SInt(23.W)) // Vector of 5 23-bit signed integers.
  val flag = Bool()
  val f = new MyFloat // Previously defined bundle.
}

BigBundle is a "type" just like Vec(5, SInt(23.W)) is a "type."

If you wish to use these types you can create a Wire of one of these types, eg.

val myVecWire = Wire(Vec(5, SInt(23.W)))
val myBundleWire = Wire(new BigBundle)

EDIT: Updated for modern chisel3 style