According to the architecture overview document Aarch64 supports 4k and 64k pages. Some CPUs also support 16k pages. Looking into address translation scheme details I come to the conclusion that such CPUs don't support the simultaneous existence of different-sized pages (unlike x86_64 which allows that). Am I right?
You're conflating two different, albeit related, things here - page size vs. granularity.
In AArch64, you have 3 possible translation granules to choose from, each of which results in a different set of page sizes:
The translation granule defines various properties of the translation regime in general, so it applies to a whole set of tables and you are correct in the sense that you can't mix and match granules within a table, although it's perfectly fine to use different granules for different tables at the same time (e.g. at different exception levels).
Comparatively, x86 always has 4KB granularity, but the range of page sizes on offer varies depending on the mode:
In both cases, the page sizes larger than the basic granule represent block entries at intermediate table levels. In other words, using the common 4KB granule, 3-level*, example:
* Depending on the actual address space size, there may be a zero'th-level table above this, but neither architecture allows block entries at that level (they would be impractically huge anyway). For AArch64 the larger granules only support block/page entries at level 2 and 3, and the 64KB granule never has a level 0 at all.
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