Simple makefile for C/C++ targets used with arm-linux-gcc

Question

I would like to cross-compile a simple program for ARM architecture using the arm-linux-gcc suite of compilers [arm-linux-gcc (Buildroot 2011.08) 4.3.6]. I've attempted to use a simple makefile for compiling C code, and another simple makefile for compiling C++ code. For example, my makefile for C code is reproduced below, but it does not create an ELF binary for running on my embedded system. The host system is x64 GNU Linux.

Here is the listing of my very simple makefile for a C program:

CC=arm-linux-gcc
CFLAGS=-Wall
main: test.o 

clean:
    rm -f test test.o 

The makefile reproduced above only creates an object file with extension .o, and does not create an ELF binary.

I've Googled for a good solution, but I can't seem to find one webpage showing example cross-compile ARM makefiles for both C and C++ programs. Perhaps an answer to this post could show such examples.

Answer 1

Have a look at the GNU make manual (info make), Section 10.2. It has a catalogue of the implicit rules, i.e. the rules where you don't need to explicitly state the commands. Like @GregHewgill thought, the "Linking a single object file" implicit rule builds N from N.o, but the name must match. Therefore, you can either name your executable like your object file, in which case

test:

or (more standard because it defines the all target)

all : test

completely suffice. You can also write out the rule explicitly, like Greg Hewgill also described. In this case, the standard rule is:

 $(CC) $(LDFLAGS) N.o $(LOADLIBES) $(LDLIBS)

Include the LDFLAGS and LDLIBS in your Makefile, it makes life easier for users.

(sic: I think LOADLIBES is really LOADLIBS, and the author missed the -o).

Overall, I'd recommend autoconf and automake instead of hand-rolling makefiles. Gives you a bunch of Makefile features for very little work.