I'm trying to learn GNUMake for a small project I'm working on. So far, even the "basic" tutorials seem pretty rough and I've yet to make sense of the makefile syntax.
Does anyone have some good resources for an absolute beginner to get familiar with GNUMake?
GNU Make is a tool which controls the generation of executables and other non-source files of a program from the program's source files. Make gets its knowledge of how to build your program from a file called the makefile, which lists each of the non-source files and how to compute it from other files.
GNU Make in Detail for Beginners | Open Source For You.
GNU Make is a program that automates the running of shell commands and helps with repetitive tasks. It is typically used to transform files into some other form, e.g. compiling source code files into programs or libraries. It does this by tracking prerequisites and executing a hierarchy of commands to produce targets.
The definitive guide is http://www.gnu.org/software/make/manual/make.html
There is an o'reilly book "Managing Projects with GNU Make" which has more explanation.
You can also uses the earlier editions, they don't cover GnuMake specifically but are a lot thinner.
Make is a dirty secret among developers - none of us understand it, we just borrow a make script from somebody else and change it. I imagine only one script was ever written from scratch (probably by the creator of the tool).
When you need to do more than the simple example most people either switch to a more modern build system like Ant or roll their own in Perl/Python/etc.
The most commonly used features of make can be broken down into a couple simple concepts, targets, dependencies and variables.
Targets are the things you want to build, but the command(s) beneath a target can be compiler commands or scripts. Generally each target refers to a module in your code, but you can make these as granular as you want to suit your project.
Dependencies are files or other targets in your project. The best example of this is for a C project where you're building a binary from a bunch of object files. Each object file will need to exist before you can build the binary, so make will traverse your targets until all of the dependencies have been completed, and then run the command for the overall target.
Variables aren't always necessary, but are pretty handy for handling things like compiler flags. The canonical examples are CC and CCFLAGs which will refer to the compiler your using i.e. gcc and the flags like -ansi -Wall -o2.
A couple more general tips and tricks:
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