Reading OUT ports for debugging

Question

I have a FIFO which has an interface that looks something like this:

entity fifo is
    port (
    CLK               : IN  std_logic := '0';
    DIN               : IN  std_logic_vector(31 DOWNTO 0);
    ALMOST_EMPTY      : OUT std_logic;
    ALMOST_FULL       : OUT std_logic;
    DOUT              : OUT std_logic_vector(31 DOWNTO 0);
    ...
    WR_ACK            : OUT std_logic
);
end fifo;

This interface is given, and I can't change iy. For debugging purposes, I want to see what is written and read to/from the FIFO. In other words, ideally I would like to assign two debug the in and out values of the FIFO, i.e.,

  DBG_FIFO_IN  <= DIN;
  DBG_FIFO_OUT <= DOUT;

For obvious reasons, the second assignment gives me the following error message:

[exec] ERROR:HDLParsers:1401 - Object DOUT of mode OUT can not be read.

I am wondering if there is any way how I can assign the DOUT value to my debug symbol. The interface is given, so I can't make DOUT an inout signal.

Answer 1

You have to assign the fifo output to a local signal you can read, then assign that signal to the output (or assign them both in parallel):

DBG_FIFO_OUT <= (your logic here);
DOUT         <= DBG_FIFO_OUT;

or

DBG_FIFO_OUT <= (your logic here);
DOUT         <= (your logic here);