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Is there a good IDE to work with VHDL projects ? Or are most of the professionals working with emacs/vim/notepad++ ?
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Design and Verification Tools (DVT) IDE for e, SystemVerilog, VHDL, and PSS. Design and Verification Tools (DVT) is an integrated development environment (IDE) for the design and verification engineers working with SystemVerilog, Verilog, VHDL, e, UPF, CPF, SLN, PSS, SDL.
VHDL is definately not dead. It competes with the language Verilog (or more accurately, with Verilog's Sucessor, SystemVerilog). My understanding is that for whatever reason historically VHDL was the more common language for FPGA design, and the reverse for ASIC design.
The syntax is different (with Verilog looking very much like C, and VHDL looking more like Pascal or Ada), but basic concepts are the same. Both languages are easy to learn, but hard to master. Once you have learned one of these languages, you will have no trouble transitioning to the other.
V4P - VHDL for Professionals. This extension provides full VHDL (2008) programming language support for Visual Studio Code.
I use Emacs+VHDL-mode which is great if you don't mind (or have already climbed) the learning curve of Emacs.
Alternatively, you could try Sigasi-HDT which is Eclipse-based and has more GUI. And some more powerful refactoring tools by the look of it.
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I have been using Sigasi HDT since it was released in january (I think) and am very pleased with it so far. Previously I used Vim for all my editing (C or VHDL), but since I switched to Sigasi I have not looked back. The Eclipse based plugin is much more than just syntax highlighting. The auto-completion of components and entities is a real time-saver and you avoid a lot of errors. You can download a free trial from their website (http://www.sigasi.com) and I encourage you to give it a try with grlib (http://www.gaisler.com) to see the real power of the plugin.
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