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The linux kernel (and various other projects including git) have very nice makefiles that hide the giant cc calls into nice little acronyms.
For example:
gcc -O2 -o cool.o cool.c -llib
gcc -O2 -o neat.o neat.c -llib
would become:
CC cool.c
CC neat.c
Which is really nice if you have a project with a large number of files and long compiler flags. I recall that this had to do with suppressing the default output and making a custom one. How do you do it?
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$@ is the name of the target being generated, and $< the first prerequisite (usually a source file). You can find a list of all these special variables in the GNU Make manual.
To use it, just set the list of variables to print on the command line, and include the debug target: $ make V="USERNAME SHELL" debug makefile:2: USERNAME = Owner makefile:2: SHELL = /bin/sh.exe make: debug is up to date. Now you can print variables by simply listing them on the command line.
A makefile is useful because (if properly defined) allows recompiling only what is needed when you make a change. In a large project rebuilding the program can take some serious time because there will be many files to be compiled and linked and there will be documentation, tests, examples etc.
You can prepend @ to calls in the makefile targets.
E.g.:
%.o: %.c
@$(CC) $(CFLAGS) -c -o $@ $<
@echo "CC $<"
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