PoU and PoC in cache maintenance operations in arm

Question

When reading ARM arch. ref. manual v7, I've found two concepts; point of coherency (PoC) and point of unification (PoU).

For PoC, it looks like the point that all agents (i.e., CPU cores) can see the same copy of memory.

For PoU, it looks like the point that all agents (in this case, CPU cores and MMU) can see the same copy of memory.

I have several follow up questions:

1. Is my understanding correct?

2. If so, If I issue DCCMVAC (Data cache clean MVA to PoC) with giving MVA to 0x40000000, (and let say PoC happen to be 0x70000000),

   all cache entries between VA of 0x40000000 and 0x70000000 are cleaned?

3. Then, if I issue DCCMVAC with MVA 0x0, all data cache entries are cleaned?

4. PoU sounds like that MMU itself has its own data caches (not TLB) for page table walk inside main memory. Is this correct?

Answer 1

According to ARM training materials:

The PoU (Point of Unification) for a processor is the point (physical location within the hardware) where the instruction and data caches and the translation table walks of the processor are guaranteed to see the same copy of a memory location. For example, a unified level 2 cache would be the point of unification in a system with Harvard level 1 caches and a TLB (to cache page table entries). If no external cache is present, main memory would be the Point of unification.

The PoC (Point of [system] Coherency) is the point at which all blocks (for example, CPUs, DSPs, or DMA engines) which can access memory, are guaranteed for a particular address to see the same copy of a memory location. Typically, this will be the main external system memory.