At the company I'm currently working for, several IDEs are being used (they develop firmware for different embedded platforms). All their C projects use a Makefile, so we decided to also add rules to their default Makefile to run static code analysis tools.
One of the IDEs they use is Eclipse.
Here we have added additional targets to the Make Target view, that triggers the lint
target from the Makefile, for example.
Since we use multiple IDEs we can tell the tools called by the Makefile to generate specific output for the IDE being used.
For Eclipse we do this by adjusting the Build Command and adding something like IDE_ENV=eclipse
to the end.
This works just fine.
Recently one of the engineers mentioned that it would be really helpful if he could run the tools, as defined in the Makefile, for a single file.
So, I updated the Makefile and it now accepts a variable SOURCE_FILE
with the path of the file that needs to be checked.
In Eclipse I tried adding SOURCE_FILE=${selected_resource_loc}
and just SOURCE_FILE=${resource_loc}
, but these variable do not seem to work when running a Make Target.
I also tried to use $(selected_resource_loc)
and $(resource_loc)
directly in the Makefile, but without any luck.
Can somebody tell me how I can pass the current selected file to Make when running a target from the Make Target view?
Some Eclipse special variables can be not recognized in a build configuration. Instead of running build procedure try to use External Tools Configuration.
Similar problem was described here: Custom command for Eclipse on current file .
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