packed vs unpacked vectors in system verilog

Question

Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:

node [range_hi:range_lo]x; 

and others that are defined like this:

node y[range_hi:range_lo]; 

I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means.

What is the difference between packed and unpacked vectors in System Verilog?

Edit: Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array? Are there any times when I shouldn't or can't use packed signals?

Answer 1

This article gives more details about this issue: http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.

A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

Answer 2

Before knowing what exactly packed and unpacked arrays are, lets also see how you can know which array is what, just by their declaration. Packed arrays have an object name comes before size declaration. For example:

bit [3][7] a; 

Unpacked array have an object name comes after size declaration. For example:

bit a[3]; 

Packed array make memory whereas Unpacked dont. You can access/declare unpacked array like this also

reg unpacked_array [7:0] = '{0,0,0,0,0,0,0,1}; 

You can mix both packed and unpacked array to make a multidimensional memory. For example:

bit [3:0][7:0]a[2:0]. 

It makes an array of 4 (i.e. 4*8) bytes with depth of 3.