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I am setting a variable in a makefile like this:
SOMEVAR = foo
This makefile later includes some other makefile in which the actual building of programs takes place:
include generic/Makefile.common
So no build targets are defined in the first makefile, it's only setting up variables which are then used by the common generic makefile to do the actual package building.
Now I know that I should be careful when using foo, so to remind myself of this, I want to print a warning message whenever this makefile is used to setup the make process. The problem is that I cannot just insert an echo command after the variable definition, because we are not yet building something there.
Is there a solution (more elegant than adding a fake target where the message is printed which would destroy the separation of setting variables and building)?
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?= indicates to set the KDIR variable only if it's not set/doesn't have a value. For example: KDIR ?= "foo" KDIR ?= "bar" test: echo $(KDIR) Would print "foo"
The $@ and $< are called automatic variables. The variable $@ represents the name of the target and $< represents the first prerequisite required to create the output file. For example: hello.o: hello.c hello.h gcc -c $< -o $@
$$ means be interpreted as a $ by the shell. the $(UNZIP_PATH) gets expanded by make before being interpreted by the shell.
= defines a recursively-expanded variable. := defines a simply-expanded variable.
SOMEVAR = foo
$(warning be careful with foo)
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