NULL statement in VHDL

Question

What is the actual purpose of null statement in VHDL? Consider the following codes

1-

CASE s IS
BEGIN
     WHEN 0 =>    y <= 0;
     WHEN 1 =>    NULL;
END CASE;

2-

CASE s IS
BEGIN
     WHEN 0 =>    y <= 0;
END CASE;

In the second code, since there is no assignment when s=1, then y retains it previous value. Isn't that? So, I think in both cases, the synthesizer will put a flip flop to keep the previous value of y.

Answer 1

I will quote IEEE1076-2008:

10.14 Null statement

A null statement performs no action.

null_statement ::= [ label : ] null ;

The execution of the null statement has no effect other than to pass on to the next statement.

NOTE—The null statement can be used to specify explicitly that no action is to be performed when certain conditions are true, although it is never mandatory for this (or any other) purpose. This is particularly useful in conjunction with the case statement, in which all possible values of the case expression shall be covered by choices; for certain choices, it may be that no action is required.

The VHDL language requires a statement for every choice in a case statement: or synthesis will give an error. Example implementation:

case OPCODE is
    when "001" => TmpData := RegA and RegB;
    when "010" => TmpData := RegA or RegB;
    when "100" => TmpData := not RegA;
    when others => null;
end case;