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In Makefile.in I see variable definition where an external variable name is enclosed between two @ symbols
# @configure_input@
package = @PACKAGE_NAME@
Where those external variables come from? Also, I couldn't find in GNU manual what does exactly enclosing a variable between two @ symbols mean? Is it something specific to Makefile.in?
Thank you.
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The file name of the target of the rule. If the target is an archive member, then ' $@ ' is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), ' $@ ' is the name of whichever target caused the rule's recipe to be run.
A substitution reference substitutes the value of a variable with alterations that you specify. It has the form ' $( var : a = b ) ' (or ' ${ var : a = b } ') and its meaning is to take the value of the variable var , replace every a at the end of a word with b in that value, and substitute the resulting string.
There is one way that the makefile can change a variable that you have overridden. This is to use the override directive, which is a line that looks like this: ' override variable = value ' (see The override Directive).
The ifeq directive begins the conditional, and specifies the condition. It contains two arguments, separated by a comma and surrounded by parentheses. Variable substitution is performed on both arguments and then they are compared.
It's an autoconf thing.
When ./configure finishes running, it generates and executes a file called config.status, which is a shell script that has the final value of the variable substitutions (anything declared with AC_SUBST).
Anything that is declared in AC_CONFIG_FILES is processed by config.status, usually by turning foo.in into foo.
When automake processes Makefile.am into Makefile.in, any AC_SUBST variable is automatically made available (using a declaration like FOO = @FOO@), unless it's suppressed by a call to AM_SUBST_NOTMAKE.
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