Makefile implicit rules with different directories

Question

I am following the manual in order to learn more about Makefiles, so I decided to code along and apply this example ( https://www.gnu.org/software/make/manual/make.html#Letting-make-Deduce-the-Recipes ) to the Makefile of my project.

The problem is that I have a seperate directory for the object files that will be generated, as far as my understanding goes the implicit rules will only look for the corresponding .c files in the same directory as the object file.

My makefile looks like this:

objects = $(addprefix objs/, main.o interface.o \
      build.o requests.o parse.o configure.o)

output: $(objects)
    gcc -o output $(objects)


objs/main.o: interface.h build.h requests.h parse.h configure.h
objs/interface.o: interface.h
objs/build.o: build.h
objs/requests.o: requests.h
objs/parse.o: parse.h
objs/configure.o: configure.h

.PHONY: clean
 clean:
    rm output $(objects)

My object files are supposed to go to the objs/ directory the source code files are located in the root directory of the project, like this:

objs/
*.c
*.h

How can I still use implicit rules without having to compile object files into the source file directory?

Answer 1

You just have to define your own implicit rule, since the built-in rules won't do that for you.

Try:

obj/%.o : %.c
        $(COMPILE.c) $(OUTPUT_OPTION) $<