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The command section of a makefile rule may recursively call "make". We can use this to organize a multipart project, or set of projects, into a set of subdirectories which each have their own makefile.
$@ is the name of the target being generated, and $< the first prerequisite (usually a source file). You can find a list of all these special variables in the GNU Make manual.
Hey, I have a simple "master" Makefile who simply calls other makefiles. I'm trying to do the following in order to build components in the right order:
LIB_A = folder_a
LIB_B = folder_b
LIB_C = folder_c
MY_TARGETS = $(LIB_A) $(LIB_B) $(LIB_C)
.PHONY: $(LIB_A)
$(LIB_A):
@$(MAKE) -C $@;
.PHONY: $(LIB_B)
$(LIB_B):
@$(MAKE) -C $@;
.PHONY: $(LIB_C)
$(LIB_C): $(LIB_A) $(LIB_B)
@$(MAKE) -C $@;
.PHONY: all
all: $(MY_TARGETS)
However, when I make, only LIB_A gets built.
(I don't even get a folder_b up-to-date message or whatever).
Any hint ?
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