Make adds unexpected mv command

Question

I'm using a makefile to build my flex/bison project. I'm having problems as it is adding a call to yacc and a mv command thus overwriting one of my files.

user@dk ~/calc ±master⚡ » make clean                                                                  
rm -rf lex.yy.c calc.tab.h calc.tab.c calc
user@dk ~/calc ±master » make
bison -d calc.y
flex calc.lex
g++ -o calc calc.tab.c lex.yy.c calc.c
user@dk ~/calc ±master⚡ » make clean
rm -rf lex.yy.c calc.tab.h calc.tab.c calc
user@dk ~/calc ±master » touch calc.y
user@dk ~/calc ±master » make
bison -d calc.y
flex calc.lex
yacc  calc.y
mv -f y.tab.c calc.c
g++ -o calc calc.tab.c lex.yy.c calc.c
... Failure ...

I simplified the makefile to the bare minimum to reproduce this. Using bison to create two files: calc.tab.c and calc.tab.h. I do not have the .h file as a target as I'm not sure what the correct way to do that is. The call to bison will generate both of the calc.tab.* files so that is not my main concern.

What is the correct way to structure this makefile to avoid the calls to yacc and mv from being generated?

calc: calc.tab.c lex.yy.c calc.c
    g++ -o calc calc.tab.c lex.yy.c calc.c

calc.tab.c: calc.y
    bison -d calc.y

lex.yy.c: calc.lex calc.tab.h
    flex calc.lex

clean:
    rm -rf lex.yy.c calc.tab.h calc.tab.c calc

Answer 1

The mv comes from make's built-in rules, which contain:

%.c : %.y
    $(YACC.y) $<
    mv -f y.tab.c $@

It looks like make is trying to create calc.c from calc.y. Some solutions to this are to redefine that rule yourself, or rename calc.y to something that won't trigger that rule for calc.c, or disable make's built-in rules.

You can list all built-in rules with make -p.