Inheritance-like feature for interfaces

Question

A great feature of SystemVerilog is inheritance, which AFAIK is limited to classes.

I was wondering if there is a way to mimic inheritance and overloading for interfaces.

For example, suppose interface2 has all signals defined in interface1 pluse sig1001 and modport2. What is the best way of defining interface2 without rewriting everything?

interface interface1;
   logic sig1;
   ...
   logic sig1000;

   modport modport1(....);
   task task1;
   ...
   endtask
endinterface

interface interface2;
   logic sig1;                    //similar to interface1
   ...
   logic sig1000;                 //similar to interface1
   logic sig1001;

   modport modport1(....);        //similar to interface1
   modport modport2(....);

   task task1;                   //similar to interface1
   ...
   endtask
endinterface

I need it to be synthesizable. My goal is not to maintain several interfaces as my code evolves I was thinking of defining a parameter and use if/generate. Any ideas are welcome.

Answer 1

There is no way to compose a SystemVerilog interface from other interfaces either by using inheritance or encapsulating them hierarchically. The only way to achieve something similar is to put sections of the interface in separate files and `include them as needed.

If you need to do this for a testbench, then you are better off using classes instead.