Verilog bitwise or ("|") monadic

Question

I've seen Verilog code where the bitwise or operator ("|") is used monadic. What's the purpose?

For example

| address[15:14]==0

or

|address[15:14]? io_din : ramrd

Cann't we omit the "|" in these cases?

Answer 1

In this case it acts as a reduction operator, for example:

|4'b1000 => 1'b1 (OR)
&4'b1000 => 1'b0 (AND)
^4'b1000 => 1'b1 (XOR)

|4'b0000 => 1'b0
&4'b1111 => 1'b1
^4'b1111 => 1'b0

ORing the entire bus to a 1 bit value, or applying an AND/XOR to the entire bus.

This is referred to as a 'unary' operator as it only take a right hand argument. They are covered in Section 11.4.9 of SystemVerilog IEEE1800-2012.

Answer 2

|address[15:14]? io_din : ramrd

is the shortcut for writing

(address[15] | address[14]) ? io_din : ramrd

i.e bitwise ORing of all bits of the bus together to generate a 1bit value. In this case it will evaluate as HIGH if either(or both) bit 15 OR bit 14 is HIGH.

similarly you can write other bitwise operators

&address[15:14]? io_din : ramrd   // ANDing

^address[15:14]? io_din : ramrd   // XORing