Verilog array syntax

Question

I'm new to Verilog, and am having a lot of trouble with it. For example, I want to have an array with eight cells, each of which is 8 bits wide. The following doesn't work:

reg [7:0] transitionTable [0:7];
assign transitionTable[0] = 10;

neither does just doing transitionTable[0] = 10; or transitionTable[0] = 8'h10; Any ideas?

(In case it is not obvious and relevant: I want to make a finite state machine, and specify the state transitions in an array, since that seems easier than a massive case switch.)

Answer 1

When using assign you should declare the array as a wire instead of areg.