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New posts in x86

GCC wrongly optimizes a pointer-equality test for a variable at a custom address

c gcc optimization x86 x86-64

Are the Linux/SMP spinlocks unnecessarily slow?

x86 linux-kernel spinlock

Intel 64 and IA-32 | Atomic operations including acquire / release semantic

assembly locking x86 intel memory-fences

On x86 if [mem] is not 32-bit aligned, can "lock inc [mem]" still work fine?

multithreading assembly x86 multiprocessing

jmp FWORD PTR [eax-0x67]?

assembly x86

x86 Assembly Force Cache Store

c caching assembly x86

Assembly language using shl to multiply by an odd number?

assembly x86

How does endianness work with SIMD registers?

x86 sse endianness simd

Does QEMU emulate TLB?

x86 qemu emulation tlb device-emulation

What is lifetime of variable inside block?

c++ c memory x86 stack

How to switch from real mode to protected mode after bootloader?

x86 operating-system bootloader protected-mode real-mode

Is the example in the membarrier man page pointless in x86?

linux x86 memory-barriers memory-model

LFENCE is really useless vs. Spectre #2?

assembly memory x86 x86-64 cpu-architecture

what is jmpl instruction in x86?

assembly x86 gnu-assembler att

BMI for generating masks with AVX512

x86 simd avx512 bmi

Why was NOP assigned to 0x90 in x86 assembly?

assembly x86 opcode machine-code nop

transpose for 8 registers of 16-bit elements on SSE2/SSSE3

assembly matrix x86 sse simd

How do I atomically read a value in x86 ASM?

assembly x86 thread-safety atomic

x86 128-bit atomic ops

assembly x86 atomic x86-64

Assembly - shr instruction turn on carry flag?

assembly x86
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