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New posts in x86
Why does the BIOS entry point start with a WBINVD instruction?
Aug 21, 2022
assembly
x86
boot
bios
intel
How to rotate an SSE/AVX vector
Oct 11, 2018
c
x86
sse
intrinsics
avx
Floating multiplication performing slower depending of operands in C
Oct 30, 2022
c
performance
x86
floating-point
stencils
intel
Why do some SSE "mov" instructions specify that they move floating-point values?
Sep 14, 2022
assembly
x86
sse
Is it possible to call a non-exported function that resides in an exe?
May 04, 2018
c
windows
assembly
x86
reverse-engineering
Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures?
Dec 27, 2018
performance
assembly
x86
intel
Difference between lea and offset
Sep 14, 2022
assembly
x86
masm
tasm
"cpuid" before "rdtsc"
Oct 05, 2022
assembly
x86
rdtsc
What is %gs in Assembly
Sep 13, 2022
linux
assembly
x86
thread-local-storage
memory-segmentation
Choice between aligned vs. unaligned x86 SIMD instructions
Aug 11, 2022
x86
sse
simd
avx
avx512
Is there an `x86` instruction to tell which core the instruction is being run on?
Sep 13, 2022
assembly
x86
x86-64
SSE multiplication of 4 32-bit integers
Jun 27, 2021
x86
sse
simd
multiplication
sse2
What is the difference between the ADC and ADCX instructions on ia32/ia64?
Aug 15, 2019
assembly
x86
Trying to understand gcc's complicated stack-alignment at the top of main that copies the return address
Sep 13, 2022
linux
gcc
assembly
x86
compiler-construction
How encode a relative short jmp in x86
Apr 01, 2022
assembly
x86
x86-64
intel
What are "non-virtualizable" instructions in x86 architecture?
Aug 20, 2017
x86
intel
virtualization
computer-architecture
xen
Why are there only four registers?
Jul 27, 2018
x86
cpu-architecture
x86 MUL Instruction from VS 2008/2010
Sep 28, 2022
c++
visual-studio
compiler-construction
assembly
x86
intel
How to count clock cycles with RDTSC in GCC x86? [duplicate]
Sep 15, 2022
c++
c
gcc
x86
rdtsc
intel
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