Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in cpu-architecture

MSI/MESI: How can we get "read miss" in shared state?

cpu-architecture cpu-cache

StoreLoad Memory Barrier

java multithreading concurrency cpu-architecture java-memory-model

Store forwarding Address vs Data: What the difference between STD and STA in the Intel Optimization guide?

performance assembly optimization intel cpu-architecture

Why wasn't MASKMOVDQU extended to 256-bit and 512-bit stores?

caching x86 intel cpu-architecture

Small branches in modern CPUs

performance x86-64 cpu-architecture avx branch-prediction

32-byte aligned routine does not fit the uops cache

performance assembly x86 intel cpu-architecture

Does this prefetch256() function offer any protection against cache timing attacks on AES?

c cpu-architecture volatile cpu-cache timing-attack

How to clear L1, L2 and L3 caches?

c++ performance caching cpu cpu-architecture

Does the Meltdown mitigation, in combination with `calloc()`s CoW "lazy allocation", imply a performance hit for calloc()-allocated memory?

performance memory-management cpu-architecture calloc page-fault

How "lock add" is implemented on x86 processors

c++ assembly x86 atomic cpu-architecture

How does a hardware trap in a three-past-the-end pointer happen even if the pointer is never dereferenced?

c++ cpu-architecture pointer-arithmetic hardware-traps

MIPS (curiosity) faster way of clearing a register?

performance assembly mips cpu-architecture micro-optimization

Program Counter?

assembly cpu mips cpu-registers cpu-architecture

Unable to disable Hardware prefetcher in Core i7

linux cpu-architecture microprocessors prefetch msr

Virtually indexed physically tagged cache Synonym

caching operating-system cpu-architecture cpu-cache

What is a circular shift with extend used for?

assembly bit-shift cpu-architecture instruction-set 68000

Is it possible to get the native CPU size of an integer in Rust?

optimization rust cpu-architecture bigint

Where data goes after Eviction from cache set in case of Intel Core i3/i7

x86 intel cpu-architecture processor cpu-cache

Why use SIMD if we have GPGPU? [closed]

cuda gpgpu simd computer-architecture cpu-architecture

Purpose of the .bin directory within node_modules? What are binaries?

node.js npm node-modules cpu-architecture
« Newer Entries Older Entries »