Bus notation in verilog

Question

I always thought that bus notations is annotated like this:

input bus[MSB:LSB]

where MSB >= LSB.

But recently, I was told that even this is possible:

wire LSB >= MSB.

Is it even true?

If so, then how come synthesizer tools get the bus size and all? Do they consider that whichever index is big is MSB?

Answer 1

Yes, both directions of bit numbering could be used in declarations. However, the same ordering must be used when you do bit selection. For example

wire [0:15] bus;
reg  [15:0] data;
assign bus [3:6] = data[3:0];

In most cases through industry the second notation is used (msb > lsb) and it is encouraged for consistency reasons. However in some situations it is convenient to do the opposite.