Incrementing Multiple Genvars in Verilog Generate Statement

Question

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in a single generate loop. I'm trying the following:

genvar i,j;
//Level 1
generate
  j=0;
  for (i=0;i<128;i=i+1)
  begin: level1Comp
    assign ci1[i] = minw(tc[j],tc[j+1]);
    j = j+2;
  end
endgenerate

And getting the following error:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "encoder.v", 322: token is '='
    j=0;

Anyone know how to increment multiple genvars in the same generate statement? Or at least get equivalent functionality?