Illegal sequential statement error

Question

please can anyone tell me how to fix this code?

what is the Illegal_sequential_statement error(in modelSim)?

why it say that near when nead ';' (in quartus) ?

LIBRARY ieee ;
USE ieee.std_logic_1164.all;

ENTITY Shift_reg IS
PORT( Par_LD: IN std_logic_vector(7 DOWNTO 0);
      Serial_In: IN std_logic;
      Serial_Out:OUT std_logic;
      RST, LD, EN, CLK: IN std_logic);
END Shift_reg;


ARCHITECTURE shiftRegARCH OF Shift_reg IS 

SIGNAL TEMP_REG : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TEMP_SOUT : STD_LOGIC;

BEGIN

process(CLK,RST)
  BEGIN 

    TEMP_REG <= (OTHERS => '0') WHEN (RST = '1') ELSE 
                 Par_LD WHEN (EN = '0' AND LD = '1')ELSE
                (Serial_In & TEMP_REG(7 DOWNTO 1)) WHEN (EN = '1')ELSE
                TEMP_REG ;                
    TEMP_SOUT <= TEMP_REG(0) WHEN (EN = '1') ELSE TEMP_SOUT;
    Serial_Out <= TEMP_SOUT;
  END PROCESS;


END shiftRegARCH ;

Answer 1

The conditional signal assignment

    TEMP_REG <= (OTHERS => '0') WHEN (RST = '1') ELSE
             Par_LD WHEN (EN = '0' AND LD = '1')ELSE
            (Serial_In & TEMP_REG(7 DOWNTO 1)) WHEN (EN = '1')ELSE
            TEMP_REG ;

is only valid with VHDL 2008. You probably have your compiler settings set to VHDL 2002 or VHDL 93