#ifdef and conditional compilation with Makefile

Question

Prior to asking I had saw this, tried but didn't help : conditional compliation based on variable into makefile

In my case my src_file.c contains:

#ifndef WITH_ATS
#define WITH_ATS
#include "ats.h"
#endif

And Makefile has:

ifdef WITH_ATS
INCLUDEDIR += -I../at2_build/include/
LDFLAGS += -L$(AT2) -lat2 -Wl,-rpath=$(AT2)
CFLAGS += -DWITH_ATS
endif

What I am trying is, if I do make WITH_ATS=1 file should compile with compiled ats lib, whereas if do make WITH_ATS=0 compilation should be without ats lib.

Any help will be appreciated.

Answer 1

Makefile

The variable WITH_ATS is not empty when running make WITH_ATS=0, and therefore ifdef WITH_ATS in the makefile evaluates to true (i.e., not what you expect).

What you actually need is to check whether WITH_ATS is equal to 1. This can be achieved by means of ifeq:

ifeq ($(WITH_ATS),1)
INCLUDEDIR += -I../at2_build/include/
LDFLAGS += -L$(AT2) -lat2 -Wl,-rpath=$(AT2)
CFLAGS += -DWITH_ATS
endif

---

C source file

In your src_file.c you need neither #ifndef nor #define. What you are implementing that way is an include guard, which is not what you want, what you actually need is:

#ifdef WITH_ATS
#include "ats.h"
#endif

That is, to include ats.h if WITH_ATS is defined.

Note that, in your C source file, WITH_ATS is just an empty macro (i.e., it doesn't have any value associated), whereas in your makefile, WITH_ATS is a variable that takes the value passed at the command line, e.g., 0 for make WITH_ATS=0.