Let's say I have a multidimensional array:
logic [7:0] mda [7:0];
What I'm now trying to do, is assigning mda[7:4] to an output port, i.e. defined as follow:
output [31:0] odata;
Of course, I can do it by using concatenation:
assign odata = {mda[7], mda[6], mda[5], mda[4]};
But there should be (and probably is) an easier way to do this. The first try would be:
assign odata = mda[7:4];
which is wrong, because types (unpacked <-> packed array) don't match. All my tries of casting (e.g. 32'(mda[7:4])) failed. Question is: what is the best way to assign that slice to an output port?
You can use a for loop... Most synthesis tools have no trouble with for loops over constant ranges:
module dut(output [31:0] odata);
logic [7:0] mda [7:0];
reg[31:0] data;
always @* begin
data = 0;
for(int i=7; i >=4; i--) begin
data <<= 8;
data |= mda[i];
end
end
assign odata = data;
endmodule
Here's a quick test: http://www.edaplayground.com/x/GfM
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