My question is deceptively simple, but I have lost several hours of study trying to get the solution. I'm trying to create a Makefile that builds an executable for each .c file in a directory.
I have tried the following:
CC = gcc
SRCS = $(wildcard *.c)
OBJS = $(patsubst %.c,%.o,$(SRCS))
all: $(OBJS)
$(CC) $< -o $@
%.o: %.c
$(CC) $(CPFLAGS) -c $<
but this way it is creating only .o
files, and not any executables. I need a rule that makes an executable for each of these .o
files. Something like the following:
gcc src.o -o src
rob's answer doesn't seem to work on my machine. Perhaps, as the complete Makefile:
SRCS = $(wildcard *.c)
all: $(SRCS:.c=)
.c:
gcc $(CPFLAGS) $< -o $@
(The last two lines, are on my machine, unnecessary, as the default rules are adequate.)
Your all
is telling it just to build the object files. Add something like
EXEC = $(patsubst %.c,%,$(SRCS))
all: $(EXEC)
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