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how to force recompile when changing Makefile flags?

Tags:

c++

c

gcc

g++

I am compiling some project with dependency so i won't have to recompile each time, but when i am adding -Dsome_flags to my CFLAGS, it is not recompiling.

dep: $(CPPS)
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

i add to my CFLAS -DDEBUG_FLAG and it forces me to do make clean and make instead of make.

like image 352
shd Avatar asked Apr 26 '15 12:04

shd


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3 Answers

It won't recompile because you don't have the makefile itself listed as a dependency.

dep: $(CPPS) Makefile
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

That said, if you're feeding in make flags from the command line (e.g. CFLAGS=-O3 make all), make has no way of detecting that you've changed those and forcing a full build.

like image 156
Mike DeSimone Avatar answered Nov 01 '22 09:11

Mike DeSimone


The simplest, in my opinion, would be to do a make clean and then a make. This is of course assuming that you want all source files to be recompiled due to the change in compiler flags. But you seem to not like this method.

If you want to modify the makefile, you can add the name of your makefile to every rule for compiling source files, for example:

    somefile.o : somefile.cpp <makefile_name>
            $(CC) -c $(CFLAGS) somefile.cpp -o somefile.o

or

    %.o : %.c <makefile_name> 
            $(CC) -c $(CFLAGS) somefile.cpp -o somefile.o

Given the size of the project, and the number of rules involved, doing a make clean; make may be the easiest and fastest method. However, as always, you mileage my vary.

Just my $0.02 worth, hope it helps T.

like image 26
thurizas Avatar answered Nov 01 '22 09:11

thurizas


Makefile looks for changes based on the data it has. Your Makefile states the only dependencies are defined under $(CPPS).

dep: $(CPPS)
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

So the make tracks the changes only within the given list, i.e., $(CPPS). So the resolution is:

dep: $(CPPS) Makefile
    $(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep

For complete but non-complex example, here is my Makefile for a helloworld program:

OBJS = helloworld.o
default: hw

%.o: %.c Makefile
    gcc -c $< -o $@

hw: $(OBJS)
    gcc $(OBJS) -o $@

clean:
    -rm -f $(OBJS) hw

Everytime I change my makefile it gets recompile! :)

like image 34
meetrp Avatar answered Nov 01 '22 11:11

meetrp