Menu
I am compiling some project with dependency so i won't have to recompile each time, but when i am adding -Dsome_flags to my CFLAGS, it is not recompiling.
dep: $(CPPS)
$(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep
i add to my CFLAS -DDEBUG_FLAG and it forces me to do make clean and make instead of make.
352
Use the command `make' to recompile the source files that really need recompilation. Make the changes in the header files. Use the command `make -t' to mark all the object files as up to date. The next time you run make, the changes in the header files do not cause any recompilation.
Make works out dependencies between targets and their dependencies, and then looks to see whether the files exist. If they do, it asks the operating system for the time and date the file was last modified.
CFLAGS is a variable that is most commonly used to add arguments to the compiler. In this case, it define macros. So the -DPACKET_LINK is the equivalent of putting #define PACKET_LINK 1 at the top of all .c and .h files in your project.
The only way of doing that is to edit the makefile to change the options. There is no convenient way to override the options without modifying the makefile . This is where make flags come into play. Flags in make are just variables containing options that should be passed to the tools used in the compilation process.
It won't recompile because you don't have the makefile itself listed as a dependency.
dep: $(CPPS) Makefile
$(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep
That said, if you're feeding in make flags from the command line (e.g. CFLAGS=-O3 make all), make has no way of detecting that you've changed those and forcing a full build.
156
The simplest, in my opinion, would be to do a make clean and then a make. This is of course assuming that you want all source files to be recompiled due to the change in compiler flags. But you seem to not like this method.
If you want to modify the makefile, you can add the name of your makefile to every rule for compiling source files, for example:
somefile.o : somefile.cpp <makefile_name>
$(CC) -c $(CFLAGS) somefile.cpp -o somefile.o
or
%.o : %.c <makefile_name>
$(CC) -c $(CFLAGS) somefile.cpp -o somefile.o
Given the size of the project, and the number of rules involved, doing a make clean; make may be the easiest and fastest method. However, as always, you mileage my vary.
Just my $0.02 worth, hope it helps T.
26
Makefile looks for changes based on the data it has. Your Makefile states the only dependencies are defined under $(CPPS).
dep: $(CPPS)
$(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep
So the make tracks the changes only within the given list, i.e., $(CPPS). So the resolution is:
dep: $(CPPS) Makefile
$(CC) $(CFLAGS) $(INC) -M $(CPPS) > dep
For complete but non-complex example, here is my Makefile for a helloworld program:
OBJS = helloworld.o
default: hw
%.o: %.c Makefile
gcc -c $< -o $@
hw: $(OBJS)
gcc $(OBJS) -o $@
clean:
-rm -f $(OBJS) hw
Everytime I change my makefile it gets recompile! :)
34
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With
