How to create a vector of vector when I'm defining IO

Question

I'm trying to define Vector of Vector for my IO, but I'm getting an error from the chisel saying:

vec element 'Vec(chisel3.util.DecoupledIO@2b57)' must be hardware, not a bare Chisel type

The code which I've written is like the following:

//Module's argument
   ,val ArgsOut: Array[Int]
...
...

val Args = for (i <- 0 until ArgsOut.length) yield {
      val arg = Vec(ArgsOut(i), Decoupled(UInt()))
      arg
 }

 val outputArg = Vec(Args)

Answer 1

Some things to consider

1. IO ports, i.e. members of the IO Bundle, must be chisel hardware constructs, Args is a scala Vector type, it needs to be chisel Vec
2. All elements of a Vec must be the same size, mostly a consequence of the need to be able to index elements of the Vec. You have each element of Args as a Vec whos's length is determined by some the elements of ArgsOut. Vec(n, type) will not
   1. Do really mean to have a 2D Vec(Vec( of decoupled IO's?
3. Your UInt in the Decoupled has an unknown width. This is not strictly speaking an error, because Firrtl can infer the width in most situations. But again this can be a problem for the requirement that a Vec's element are all the same length. Inferred widths in IOs should be used cautiously.

I was able to construct at IOBundle like this

  val io = IO(new Bundle {
    val args = Vec(ArgsOut.length, Vec(ArgsOut(0), Decoupled(UInt(18.W))))
    val outputArg = Flipped(args)
  })

Which compiles but may not quite be what you had in mind. I was able to connect the io's using

io.outputArg <> io.args

If this doesn't seem to fit your use case, I need to know a bit more how you intend to use the fields and we should be able to figure out how to wire them up.