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Consider the following Makefile:
# <include global configuration Makefile>
INCL = -I../include \
-I<whatever>
CPPFLAGS=$(DEFS) $(INCL)
CXXFLAGS = -O0 -g -Wall -fmessage-length=0
SRCS = $(wildcard *.cpp)
OBJS = $(SRCS:.cpp=.o)
all: $(OBJS)
%.o: %.cpp
$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c -o $@ $<
depend: .depend
.depend: $(SRCS)
$(CPP) $(CPPFLAGS) -M $^ > $@
clean:
rm -f $(OBJS)
rm .depend
-include .depend
This Makefile creates an #include dependency chain using the g++ -M command, and includes it. This can be a rather long process. The problem is that this file is generated even if make clean is called, when this file would be deleted anyway. Is ther a way to conditionally include this file, and not bother creating it if the clean target is run?
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The file name of the target of the rule. If the target is an archive member, then ' $@ ' is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), ' $@ ' is the name of whichever target caused the rule's recipe to be run.
6.6 Appending More Text to Variables Often it is useful to add more text to the value of a variable already defined. You do this with a line containing ' += ', like this: objects += another.o.
The include directive tells make to suspend reading the current makefile and read one or more other makefiles before continuing. The directive is a line in the makefile that looks like this: include filenames … filenames can contain shell file name patterns.
all target is usually the first in the makefile, since if you just write make in command line, without specifying the target, it will build the first target. And you expect it to be all . all is usually also a . PHONY target.
Something like this:
ifneq ($(MAKECMDGOALS),clean)
-include .depend
endif
See the make manual page on Goals for more information
Edit: -include cannot be tab indented, otherwise it is ignored.
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