How to add two different sized vectors VHDL

Question

Hello I would like to ask, how could I add two vectors in VHDL, which one of them is 7 downto 0 and the other one is 8 downto 0. I tried something like this, but it does not work. Thank you in advance.

IS_CARRY <= '0' & (IN1 + IN2)

Answer 1

You need to extend the shorter vector to 9 bits and then do the addition.

Declarations:

signal in1 : UNSIGNED(7 downto 0);
signal in2 : UNSIGNED(8 downto 0);
signal res : UNSIGNED(8 downto 0);

Example:

res <= ('0' & in1) + in2;

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It's not recommended to use STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED. Use NUMERIC_STD instead. Doing arithmetic on STD_LOGIC_VECTORs is no good style. Use the types SIGNED and UNSIGNED for this purpose.