How is the size of TLB in Intel's Sandy Bridge CPU determined?

Question

The wiki webpage(https://en.wikipedia.org/wiki/Sandy_Bridge) mentioned that Data TLB has 64, 32 and 4 entries respectively for 4KB, 2MB and 1GB pages.

I found these numbers hard to understand. Sandy Bridge has a virtual address of 48 bits, which means for 4K page, there can be 2^36 pages, and for 2MB and 1GB pages, there should be 2^27 and 2^18 pages. If TLB has 64 entries for 4K page, the size of each entry should be no less than 6+36 = 42 bits. Why are there only 32 entries for 2M page, instead of 2^15 (42-27) entries?

I know in TLB entries there will be additional bits for control purpose. But shouldn't that space be constant for different page size?

Answer 1

Becuase they are different TLBs.
Executing cpuid with EAX=2 on my Haswell and decoding the TLB descriptors gets:

Instruction TLB:
              2M/4M pages, fully associative, 8 entries
              4KByte pages, 8-way, 64 entries

Data TLB:
              2M/4M pages, 4-way, 32 entries and a separate array with 1 GByte pages, 4-way, 4 entries
              4 KByte pages, 4-way, 64 entries

Shared 2nd-Level TLB:
              4 K/2M pages, 8-way, 1024 entries

A TLB cache is a highly specialized CAM with a fixed layout, it is not a scratch memory with a general purpose layout.

Some TLB can handle more that one page size but those are trade-offs were the information is cached in a common format.
Having different TLBs handling different page sizes improves cache hits, just like having a DTLB and an ITLB.

Data caches works differently since they don't cache information, they cache data with no layout and that's why it makes sense to give the size in KiB for them but it doesn't for caches that deal with structured information.