How eval function can be used in makefile?

Question

In the manual:

The eval function is very special: it allows you to define new makefile constructs that are not constant; which are the result of evaluating other variables and functions. The argument to the eval function is expanded, then the results of that expansion are parsed as makefile syntax.

It’s important to realize that the eval argument is expanded twice; first by the eval function, then the results of that expansion are expanded again when they are parsed as makefile syntax. This means you may need to provide extra levels of escaping for “$” characters when using eval.

the "expanded twice" confuses me.

for example, i create a makefile :

define func
    tmp = $(OBJPATH)/$(strip $1)
    objs += $$(tmp)
    $$(tmp) : $2
        gcc $$^ -o $$@
endef

all : foo

$(eval $(call func, foo, 1.c))    

how will the eval function be expanded ?

Answer 1

This has been issue for me, but I found a nice workaround. In my case it was related to AWS docker login. I had in my shell script previously:

eval $(aws ecr get-login --region eu-west-1 --no-include-email --profile someprofile)

but when putting that into Makefile it didn't work. The workaround for this is to change the line into:

$$(aws ecr get-login --region eu-west-1 --no-include-email --profile someprofile)

Answer 2

The easiest way to understand it is to replace the eval with info:

$(info $(call func, foo, 1.c))

That will display as output the result of the first expansion, so you can see what make will actually be parsing. You didn't provide the values for the OBJPATH variable, but if it was obj for example then in your case the first expansion (of the call function) results in:

tmp = obj/foo
objs += $(tmp)
$(tmp) : 1.c
    gcc $^ -o $@

Then the make parser will evaluate this, and in the process it will expand it again, so things like $(tmp) are expanded.