How does Linux scheduler of OP-TEE work after switching to Secure world

Question

I successfully run OP-TEE on QEMU and want to figure out how scheduler works. I modified the source code to get the variable jiffies right before entering Secure World and after returning to Normal World. Here is a piece of code.

i=jiffies;
tee_smc_call(&param);
j=jiffies

Here tee_smc_call is the asm function issuing SMC call. I find j will be greater 1 than i if timer interrupt results in leaving SW. I think it means the timer interrupt is handled somewhere. If my deduction is not right please correct me.

I go to the link https://lists.linaro.org/pipermail/tee-dev/2015-August/000160.html and https://github.com/OP-TEE/optee_os/issues/332. The OP-TEE developer says timer interrupt will be serviced by NW as soon as switching back to NW.
I read the source code of IRQ handler of SW. I thought the SW handler would find the VBAR of NW and change the return address to the NW handler. However I found no such code.
I have read some posts on this site TrustZone: Scheduling processes from the two worlds and ARM TrustZone - Behaviour of the scheduler in Secure and Non-Secure OS. The latter is similar to mine but the answer does not tell what happens in the OP-TEE implementation.

So I am wondering what is the magic making the timer interrupt be handled again after returning to NW because it has been service once in SW.

I am not familiar with OP-TEE. And this is my first question. Please forgive me if it is not clear or stupid. Thanks.

Answer 1

Since nobody answers my question for one year I will try to give my own explanation.

NOTE that it is just MY own understanding. I am not an expert on such things.

1. The timer interrupt is generated and GIC changes the state from inactive to pending.
2. GIC forwards the interrupt request to the processor in Secure state. This is a foreign IRQ for SecureOS.
3. The IRQ handler in SecureOS works as Forward IRQ from secure world to normal world. I look into the source code of thread_irq_handler and cannot find the read for Interrupt Acknowledge Register.
4. The processor returns to Normal World. The state of the timer interrupt is still pending according to Interrupt handling state machine in GIC architecture specification.
5. GIC will signal the interrupt request to CPU at appropriate time.
6. The interrupt is serviced in Normal World.

My chain of reasoning is like this.

Interrupt Acknowledge Register is not read in IRQ handler of Secure OS.

--> The interrupt state is still pending.

--> GIC will signal the interrupt request to CPU.