How do I use the RISC-V Vector (RVV) instructions in LLVM IR?

Question

In this presentation Kruppe and Espasa give an overview of the RISC-V Vector extension (RVV) and on slide 16 they show LLVM IR samples which use the vector instructions through intrinsic functions, such as:

%vl = call i32 @llvm.riscv.vsetvl(i32 8)

At the time of the talk (April 2019) LLVM support for the V extension was developed out-of-tree at https://github.com/hanna-kruppe/rvv-llvm. However, that repository is archived now and the README file indicates that it is outdated since support for the RISC-V V extension is now developed upstream. I assume that this means that the features are now available from LLVM master at https://github.com/llvm/llvm-project.

However, when I pull the current master and build it and try to compile the sample code with llc (specifying the target with --mtriple=riscv32-unkown-none-rv32imv), I get following error:

error: ../llvm-project/build/bin/llc: test.ll:4:18: error: use of undefined value '@llvm.riscv.vsetvl'

It seems that the V extension is available, since llc -march=riscv32 -mattr=help lists it:

Available features for this target:
...
  experimental-v           - 'V' (Vector Instructions).

Do I have to explicitly enable target features that are marked as experimental? Are these vector intrinsics shown in the slides even present in the upstream version? If yes, how do I use them? If no, how do I then use vector instructions in LLVM IR?

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Follow-up: in this post Eli Friedman explains that target-specific intrinsics should be defined in include/llvm/IR/IntrinsicsRISCV.td, and indeed in the archived out-of-tree repository that file contains some vector-specific intrinsics which are not present in the upstream version. If these intrinsics have not been ported upstream, what is then the correct way to use the RISC-V vector instructions?

Answer 1

There are only two riscv triple defined in llvm/include/llvm/ADT/Triple.h: riscv32 and riscv64.

By default HasStdExtV which is the flag corresponding to experimental-v in initialized to false in llvm/lib/Target/RISCV/RISCVSubtarget.h, if you want to use this extension you need to enable this feature.

Clangs seems also supporting this feature. In clang/lib/Driver/ToolChains/Arch/RISCV.cpp you can see that march support v feature and generate experimental-v for llc.

There is nothing in include/llvm/IR/IntrinsicsRISCV.td about Vector extension , however you can find the description of the instructions from the standard 'V' Vector extension in llvm/lib/Target/RISCV/RISCVInstrInfoV.td. It still experimental. In clang also you can find that even if the v extension is supported, in the default you can see // Currently LLVM supports only "mafdc". in clang/lib/Driver/ToolChains/Arch/RISCV.cpp