How do I convert strings to enums in SystemVerilog?

Question

I have command-line plusargs that I want to map to enumerated values.

 vsim foo +MY_PLUSARG=BAR

How do I get the string "BAR" to become the enum BAR?

Answer 1

If you are using UVM 1.2 or have access to the library, you may want to use uvm_enum_wrapper class to do the conversion. It is a template class wrapper defined in uvm_globals.svh and you can use it as follows:

typedef enum {BISTRO, COFFEE_SHOP, BAR} places_e;

typedef uvm_enum_wrapper#(places_e) places_wrapper;
places_e place;

places_wrapper::from_name("BAR", place);

Quite like the code you provided in this solution, the wrapper class works by traversing the enum entries and creating an assoc array for a enum[string] map for the given enum (supplied as template parameter). So if you are using UVM 1.2, don't repeat.