The current Makefile has something like this:
target1 : lib1.a lib2.a
target2 : lib1.a lib3.a
target3 : lib3.a
lib1.a:
$(MAKE) -C sub_dir all
I want to change this Makefile so that wherever a target depends on lib1.a
, it always run the command "$(MAKE) -C sub_dir all
", always. Another words, in the above example, target1 and target2 will always run "$(MAKE) -C sub_dir all
". Is there any way I can do that?
I know the following does not work:
target1 : lib2.a
$(MAKE) -C sub_dir all
target2 : lib3.a
$(MAKE) -C sub_dir all
target3 : lib3.a
Because if lib2.a has no update, the the command does not run. I have one restriction, I only control lib1.a, I cannot change how lib2.a is built.
Any help is appreciated!
UPDATE: I used the following solution:
target1 : lib1.a lib2.a
target2 : lib1.a lib3.a
target3 : lib3.a
lib1.a: relay
.PHONY: relay
relay:
$(MAKE) -C sub_dir all
The GNU Make help says that FORCE is not as efficient as .PHONY, but from your explanation, it seems to me FORCE is better. Do I mis-understand?
I think a Force Target
is what you are looking for here.
lib1.a: FORCE
$(MAKE) -C sub_dir all
FORCE: ;
As compared to a .PHONY
rule (as suggested by @MadScientist here) this will not in-and-of-itself force all the targets that depend on lib1.a
to rebuild all the time. It will only do that if lib1.a
actually changes.
A better solution though is likely to get rid of the sub-make entirely and actually have the dependency information for lib1.a
available to this makefile (either directly or via an included makefile in sub_dir
) because that avoids this entire "force this recipe because I can't tell you how to tell if the target needs updating" problem.
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