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I wish to define a C macro by passing it as an argument to make, which is called from the command-line.
Background: I want the directive #define ENABLE_OPT 1 to be included in my C source code when a certain build option is chosen. Thus, I want this to be done via the make command-line instead of modifying the source code or the makefile.
How can this be achieved? I find that make -DENABLE_OPT=1 -f Makefile throws errors that 'E', 'N' etc. are invalid arguments to make.
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Passing parameters to a macro. A parameter can be either a simple string or a quoted string. It can be passed by using the standard method of putting variables into shared and profile pools (use VPUT in dialogs and VGET in initial macros).
For portability, you should not have more than 31 parameters for a macro. The parameter list may end with an ellipsis (…). In this case, the identifier __VA_ARGS__ may appear in the replacement list. Function-like macro invocation: An identifier followed by a comma-separated list of arguments in parentheses.
Macro Arguments (DEFINE-! ENDDEFINE command) The macro definition can include macro arguments, which can be assigned specific values in the macro call. There are two types of arguments: keyword and positional. Keyword arguments are assigned names in the macro definition; in the macro call, they are identified by name.
To use a macro that expects arguments, you write the name of the macro followed by a list of actual arguments in parentheses, separated by commas. The number of actual arguments you give must match the number of arguments the macro expects. Examples of use of the macro min include min (1, 2) and min (x + 28, *p).
You can use --eval, which will evaluate the string as a makefile statement:
make --eval="FLAGS+= -D ENABLE_OPT=1"
The make variable FLAGS is then used as a compiler argument to compile the code.
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