Get filename without extension within makefile

Question

My makefile looks like this:

SRCS    = $(wildcard *.asm)
OBJS    = ${SRCS:.asm=.o}

# define a suffix rule for .asm -> .o
.asm.o : $(SRCS)
    nasm -f elf $<

all: $(OBJS)
    gcc -o ?? $<
           ^need the name of the target without file extension here ($* is blank)

However, $* is working within .asm.o but is blank within all. How would I go about setting the gcc output filename to the filename of the object file without any extension?

For example, I want it to execute the following (after the .o file is generated by nasm)

gcc filename filename.o

Answer 1

I think you are looking for

.PHONY: all
all: $(patsubst %.o,%,$(OBJS))
%: %.o
    gcc -o $@ $<

Your attempt would define a target all which depended on all the object files as if it contained them all; I presume you really want each object file to be independent, and for the all target to depend on them all being made.

(Technically you could now use $* because it is identical to $@ in this case, but that's just obscure.)

This is by and large isomorphic to your existing nasm rule, except when there is no suffix, you cannot use the suffix syntax. In other words, your rule is equivalent to

OBJS = $(patsubst %.asm,%.o,$(SRCS))
%.o: %.asm
    nasm -f elf $<

The only remaining difference is the .PHONY declaration which just documents that all isn't a file name.