Function and difference between $() and ${} in Makefile

Question

In makefile, ${CC} -o myfile myfile.c and $(CC) -o myfile myfile.c both work fine even without definition of CC. My question is:

1. How to use $(..) and ${..}?

• Are they just convert the string in {} or () to lowercase if that string is not defined?
• Why does $${dir} need two $$ in
  for dir in ${DIR}; do (cd $${dir}; ${MAKE}); done

2. Is there any differences between ${} and $()?

Answer 1

There is no difference between () and {} for Make.

If you use $$ in a recipe, then $ is "escaped" and passed to the shell. The shell may then make a difference between $() or ${}. But that is entirely up to the shell, and has nothing to do with Make or makefiles.

In the recipe command that you quote

for dir in ${DIR}; do (cd $${dir}; ${MAKE}); done 

Make does this:

• substitutes the value of DIR, for ${DIR}, and that could just as well have been $(DIR)
• replaces $$ with $ ("escaping", so that $ could be passed to the shell)
• substitutes the value of MAKE for ${MAKE}, again this could have been $(MAKE). The value of MAKE is automatically setup by Make, to the make executable that is being used.
• passes the resulting string to shell for execution - the shell then interprets the one remaining ${} the way it wants.

CC, similarly to MAKE is one of those variables that are by default pre-defined by Make, that's why it "works" even if you don't set it yourself.

By the way, a better way to write this recipe for "target" is

.PHONY: $(DIR) target: $(DIR) $(DIR):     $(MAKE) -C $@ 

Please consult the manual for explanation of things that are unclear.