Explicitly make a target with a variable name

Question

I have a Makefile with the following format:

.PHONY: all

target1 := file1
target2 := $(target1).txt

all: $(target2)

$(target1): prerequisite1
    recipe

$(target2): $(target1)
    recipe 

target2 depends on target1, and make will correctly substitute the strings to create the file names. However, on my system, the file names and paths are quite tedious to type out; I'm wondering if there is any way to specifically make target1 while referring to its name not as the file path, but as the variable.

For example, I would like to be able to invoke:

$ make $(target1) 

rather than

$ make path/to/file1

I want to do this because I change the variables quite a bit and the structure of my Makefile has many intermediates that are occasionally difficult to trace back to their literal file paths, but are easy to make based on the variable names that I have assigned them.

The above does not work, and I have read the man page as well as done quite a bit of searching here and on Google. Just wondering if anyone has come across this problem before and found a solution.

Answer 1

This is a bit clunky to due use of recursion, but it does what you want:

target1 := file1

$(target1):
    @echo "Hello from $@"

variable-%:
    $(MAKE) $($*)

gives

$ make variable-target1
make file1
Hello from file1