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I'm not sure I understand the difference between 'downto' vs. 'to' in vhdl.
I've seen some online explanations, but I still don't think I understand. Can anyone lay it out for me?
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And what is the difference with to ? The keywords downto and to specify the direction of ranges in VHDL. downto is descending (going down); to is ascending (going up).
The rules are a little more complex than this, but basically: you use <= to do signal assignment, which takes effect on the next delta cycle. You use := to do variable assignment, which takes place immediately. So if you have a signal, you always use <= . If you have a variable, you always use := .
A'RANGE is the range A'LEFT to A'RIGHT or A'LEFT downto A'RIGHT . A'RANGE(N) is the range of dimension N of A. A'REVERSE_RANGE is the range of A with to and downto reversed. A'REVERSE_RANGE(N) is the REVERSE_RANGE of dimension N of array A.
The "not equal" operator in VHDL is /= . In general, if you want to negate an expression, use not .
If you take a processor, for Little endian systems we can use "downto" and for Bigendian systems we use "to".
For example,
signal t1 : std_logic_vector(7 downto 0); --7th bit is MSB and 0th bit is LSB here.
and,
signal t2 : std_logic_vector(0 to 7); --0th bit is MSB and 7th bit is LSB here.
You are free to use both types of representations, just have to make sure that other parts of the design are written accordingly.
This post says something different:
"The term big endian (or little endian) designates the byte order in byte oriented processors and doesn't fit for VHDL bit vectors. The technical term is ascending and descending array range. Predefined numerical types like signed and unsigned are restricted to descending ranges by convention."
So, this answer can be confusing...
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