Determining C executable name

Question

Most C compilers provide the -o option for this, such as:

gcc -o gentext gentext.c
cc  -o mainprog -Llib -lmymath firstbit.c secondbit.o
xlc -o coredump coredump.c

-ofilename will make filename instead of a.out.

According to the manual:

-o <file>  Place the output into <file>

In Unix, where C originated from, C programs are usually compiled module-by-module, and then the compiled modules are linked into an executable. For a project that consists of modules foo.c and bar.c, the commands would be like this:

cc -c foo.c
cc -c bar.c
cc -o myprog foo.o bar.o

(With -c, the output filename becomes the source file with the suffix replaced with .o.)

This allows you to also re-compile only those modules that have changed, which can be a big time saver for big programs, but can also become pretty tricky. (This part is usually automated using make.)

For a single-module program there's not really any point in first compiling to a .o file, and then linking, so a single command suffices:

cc -o foo foo.c

For single-module programs, it is customary to call the resulting executable program the same as the C source file without the .c suffix. For multi-module programs, there is no hard custom on whether the output is named after the file with the main function or not, so you're free to invent whatever strikes your fancy.

With the -o option.

gcc main.c -o myCoolExecutable.o

This is ok if your program consists of a single file. If you have more files I suggest using make: create a Makefile and then run the command make.

A Makefile is a file containing some rules for compilation. An example can be the following (# means the line is a comment):

CXX = gcc

#CXXFLAGS = -std=c++11
#INC_PATH = ...
#LIBS = ...

SOURCEDIR := yourSourceFolder
SOURCES := $(wildcard $(SOURCEDIR)/*.c)
OBJDIR=$(SOURCEDIR)/obj

OBJECTS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.o, $(SOURCES))
DEPENDS := $(patsubst $(SOURCEDIR)/%.c,$(OBJDIR)/%.d, $(SOURCES))

# ADD MORE WARNINGS!
WARNING := -Wall -Wextra

# .PHONY means these rules get executed even if
# files of those names exist.
.PHONY: all clean

# The first rule is the default, ie. "make",
# "make all" and "make parking" mean the same
all: yourExecutableName

clean:
    $(RM) $(OBJECTS) $(DEPENDS) yourExecutableName

# Linking the executable from the object files
# $^   # "src.c src.h" (all prerequisites)
yourExecutableName: $(OBJECTS)
    $(CXX) $(WARNING) $^ -o $@
    #$(CXX) $(WARNING) $(CXXFLAGS) $(INC_PATH) $^ -o $@ $(LIBS)

-include $(DEPENDS)

$(OBJDIR):
    mkdir -p $(OBJDIR)

$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
    $(CXX) $(WARNING) -MMD -MP -c $< -o $@

Shortly CXX variable defines your compiler (gcc, g++), with CXXFLAGS you can define flags for your compilation (i.e. -std=c++11). Then you can include and define custom (INC_PATH and LIBS: not set in the example). With SOURCEDIR you can specify your source code directory (where *.c files are).Then SOURCES is basically telling that the source files for the compilation are all the files having extension *.c.

The Makefile contains a set of rules whose structure is the following:

output: inputs
    commandToExecute

The rule to generate your executable file is

yourExecutableName: $(OBJECTS)
    $(CXX) $(WARNING) $^ -o $@

which is equivalent to gcc -Wall -Wextra $(OBJECTS) -o yourExecutableName.

$(OBJECTS) are the object file resulting from the compilation. When the above rule is executed, if they are not found make will continue scanning the file to find a rule to generate them. In this case the rule to generate these files is:

$(OBJDIR)/%.o: $(SOURCEDIR)/%.c Makefile | $(OBJDIR)
    $(CXX) $(WARNING) -MMD -MP -c $< -o $@

If further information is needed let me know.

If foo will be your executable and bar.c is your source file then the command is:

gcc -o foo bar.c

Compile using:

cc -o <opfilename> <filename.c>

Execute using:

./<opfilename>