Creating a VHDL backend for LLVM?

Question

LLVM is very modular and allows you to fairly easily define new backends. However most of the documentation/tutorials on creating an LLVM backend focus on adding a new processor instruction set and registers. I'm wondering what it would take to create a VHDL backend for LLVM? Are there examples of using LLVM to go from one higher level language to another?

Just to clarify: are there examples of translating LLVM IR to a higher level language instead of to an assembly language? For example: you could read in C with Clang, use LLVM to do some optimization and then write out code in another language like Java or maybe Fortran.

Answer 1

Yes !

There are many LLVM back-end targeting VHDL/Verilog around :

• (open source) Legup paper
• (commercial) Xilinx HLS
• (online) C-to-verilog

And I know there are many others...

The interesting thing about such low-level representations as LLVM or GIMPLE (also called RTL by the the way) is that they expose static-single assignments (SSA) forms : this can be translated to hardware quite directly, as SSA can be seen as a tree of multiplexers...

Answer 2

There's nothing really special about the LLVM IR. It's a standard DAG with variable arity. Decompiling LLVM IR is a lot like decompiling machine language.

You might be able to leverage some frontend optimizations such as constant folding, but that sounds pretty minor compared to the whole task.

My only experience with LLVM was writing a binary translator for a class project, from a toy CISC to a custom RISC.

I'd say, since it's the closest thing to a standard IR (well, GCC GIMPLE is a close second), see if it fits with your algorithms and style and evaluate it as one alternative.

Note that GCC also started out prioritizing portability above all, and has also accomplished a lot.