Control Data Flow graphs or intermediate representation

Question

we are working on a project to come up with an intermediate representation for the code in terms of something called an assignment decision diagram. So it would be very helpful if someone can tell us how you guys are compiling the code and how to access the graphs generated during compilation i.e after parsing the code for grammar.

Even help regarding accessing the code after parsing of the compiler is fine. Any help regarding how to go about doing it is also appreciated.

Answer 1

Currently, there is not a well defined intermediate representation of Chisel as it goes between the user source code and the specified C++ or Verilog backends.

However, I believe this is a current project amongst the Chisel devs to break apart the backend and allow access to the IR (and allow for user-defined compiler passes).

In the meantime, check out Backend.scala (particularly the elaborate() method). That's where a lot of the magic originates. I believe it is possible to jump into the Scala command line in the middle of elaboration, which will give you access to the hardware tree representation, but I'm not sure how meaningful or useful that will be for you.