concurrent and conditional signal assignment (VHDL)

Question

In VHDL, there are two types for signal assignment:

concurrent   ---->    when...else
             ---->    select...when...else

sequential   ---->    if...else
             ---->    case...when

Problem is that some say that when...else conditions are checked line by line (king of sequential) while select...when...else conditionals are checked once. See this reference for example.

I say that when..else is also a sequential assignment because you are checking line by line. In other words, I say that there no need to say if..else within a process is equivalent to when..else. Why they assume when..else is a concurrent assignment?

Answer 1

Concurrent vs Sequential is about independence of execution.

A concurrent statement is simply a statement that is evaluated and/or executed independently of the code that surrounds it. Processes are concurrent. Component/Entity Instances are concurrent. Signal assignments and procedure calls that are done in the architecture are concurrent.

Sequential statements (other than wait) run when the code around it also runs.

Interesting note, while a process is concurrent (because it runs independently of other processes and concurrent assignments), it contains sequential statements.

Often when we write RTL code, the processes that we write are simple enough that it is hard to see the sequential nature of them. It really takes a statemachine or a testbench to see the true sequential nature of a process.