Component Instantiation vs Entity Instantiation in VHDL

Question

I have experience with Verilog/SystemVerilog but I am new to VHDL and I am trying to figure out when I should use component instantiation or entity instantiation. By component instantiation I mean the legacy way of declaring components of an entity before instantiating them. On the other hand, entity instantiation, which has been introduced with VHDL-93, allows you to declare an entity directly without specifying the component. Related Article

It seems to me that Entity Instantiation is always preferable unless you don't have an architecture implemented yet and you just want to define a black box.

This is a Related Question that I've found but it does fully address my doubts. Since it is possible to define both the generic map and the architecture for any entity:

entity work.MyEntity_E(ARCH) generic map(
...)
port map(
...
);

what is the additional flexibility of doing component instantiation? What would be the simplest example showing something that can not be done with entity instantiation but can be done with component instantiation?