Chisel -- clock gating

Question

Clock gating is important for power reduction. How do we specify clock gating in Chisel?

Clock gating is where a logic signal determines whether or not the clock to a particular register is toggled. When the logic signal is inactive, then the clock remains steady, unchanging. Only when the enable is active does the clock signal toggle, which in turn latches inputs into the flip flop.

The backend tools handle inserting the implementation of this, but they need the RTL to indicate the enable signal.

Answer 1

In my experience the backend tools do a good job of inferring clock gate enables (i.e. 95%+ of my registers in my Chisel SoC are clock gated).

Therefore I do not find myself needing to do what you ask, but if all you need is to specify the enable to a register this is easy with RegEnable.